[Series 08] Enabling Efficient Memory Systems using Novel Compression Methods

Title: Enabling Efficient Memory Systems using Novel Compression Methods

Speaker: Per Stenström

Chalmers University of Technology / ZeroPoint Technologies
Goteborg, Sweden

Date: Nov 7th, 2024 at 3:30 pm

Location: EER 3.646 or Zoom Link

Abstract:

Using data compression methods in the memory hierarchy can improve the
efficiency of memory systems by enabling higher effective cache capacity,
more effective use of available memory bandwidth and by enabling higher
effective main memory capacity. This can lead to substantially higher
performance and lower power consumption. However, to enable these values
requires highly effective compression algorithms that can be implemented
with low latency and high throughput. Research at Chalmers University of
Technology and at ZeroPoint Technologies, a fabless startup company, has
yielded many new families of compression methods that are now being
commercially deployed. This talk will present the major insights of more
than a decade of research on memory compression methods for the memory
hierarchy. The talk covers value-aware caches and statistical compression
of cache content, compression algorithms that are tuned to the data at hand
through data analysis using new clustering algorithms to allow for
substantially higher memory bandwidth and compression infrastructures
that expand capacity of main memory.

Bio:

Per Stenstrom is professor at Chalmers University of Technology. His research
interests are in parallel computer architecture. He has authored or
co-authored four textbooks, about 200 publications and twenty patents in
this area. He has been program chairman of several top-tier IEEE and ACM
conferences including IEEE/ACM Symposium on Computer Architecture and acts
as Associate Editor of ACM TACO and Topical Editor IEEE Transaction on
Computers. He is a Fellow of the ACM and the IEEE and a member of Academia
Europaea and the Royal Swedish Academy of Engineering Sciences.