In April 2023 I posted some results and comments The evolution of single-core bandwidth in multicore processors illustrating the (slow) growth in single-core memory bandwidth over time in Intel and AMD multicore processors. Here is an update to the summary chart, adding the AMD EPYC 4 (“Genoa”) processors. Genoa delivers… read more
“Memory directories” in Intel processors
One of the (many) minimally documented features of recent Intel processor implementations is the “memory directory”. This is used in multi-socket systems to reduce cache coherence traffic between sockets. I have referred to this in various presentations as: “A Memory Directory is one or more bits per cache line… read more
The evolution of single-core bandwidth in multicore processors
The primary metric for memory bandwidth in multicore processors is that maximum sustained performance when using many cores. For most high-end processors these values have remained in the range of 75% to 85% of the peak DRAM bandwidth of the system over the past 15-20 years — an amazing accomplishment… read more