Is it unimportant just because we are not talking about it? I was recently asked for comments about the value of increased bisection bandwidth in computer clusters for high performance computing. That got me thinking that the architecture of most internet news/comment infrastructures is built around “engagement” — effectively amplifying… read more
Computer Hardware
Disabled Core Patterns and Core Defect Rates in Intel Xeon Phi x200 (Knights Landing) Processors
Defect rates and chip yields in the fabrication of complex semiconductor chips (like processors) are typically very tightly held secrets. In the current era of multicore processors even the definition of “yield” requires careful thinking — companies have adapted their designs to tolerate defects in single processor cores, allowing them… read more
Mapping addresses to L3/CHA slices in Intel processors
Starting with the Xeon E5 processors “Sandy Bridge EP” in 2012, all of Intel’s mainstream multicore server processors have included a distributed L3 cache with distributed coherence processing. The L3 cache is divided into “slices”, which are distributed around the chip — typically one “slice” for each processor core. Each… read more