I have been involved in HPC for over 30 years: 12 years as student & faculty user in ocean modeling, 12 years as a performance analyst and system architect at SGI, IBM, and AMD, and over 7 years as a research scientist at TACC. This history is based on my… read more
Computer Hardware
Some notes on producer/consumer communication in cached processors
In a recent Intel Software Developer Forum discussion (https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/700477), I put together a few notes on the steps required for a single-producer, single-consumer communication using separate cache lines for “data” and “flag” values. Although this was not a carefully-considered formal analysis, I think it is worth re-posting here as a… read more
Intel discloses “vector+SIMD” instructions for future processors
The art and science of microprocessor architecture is a never-ending struggling to balance complexity, verifiability, usability, expressiveness, compactness, ease of encoding/decoding, energy consumption, backwards compatibility, forwards compatibility, and other factors. In recent years the trend has been to increase core-level performance by the use of SIMD vector instructions, and… read more