As part of my attempt to become organized in 2019, I found several draft blog entries that had never been completed and made public. This week I updated three of those posts — two really old ones (primarily of interest to computer architecture historians), and one from 2018: July 2012:… read more
Xeon Phi
A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing)
A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing) Introduction: In December 2017, my colleague Damon McDougall (now at AMD) asked for help in porting the fused multiply-add example code from a Colfax report (https://colfaxresearch.com/skl-avx512/) to the Xeon Phi x200 (Knights Landing) processors here at TACC. There was… read more
Memory Latency on the Intel Xeon Phi x200 “Knights Landing” processor
The Xeon Phi x200 (Knights Landing) has a lot of modes of operation (selected at boot time), and the latency and bandwidth characteristics are slightly different for each mode. It is also important to remember that the latency can be different for each physical address, depending on the location of… read more