• Skip to main content
  • Skip to primary sidebar
UT Shield
The University of Texas at Austin

Xeon Phi

January 9, 2019, Filed Under: Computer Architecture, Performance

New Year’s Updates

As part of my attempt to become organized in 2019, I found several draft blog entries that had never been completed and made public. This week I updated three of those posts — two really old ones (primarily of interest to computer architecture historians), and one from 2018: July 2012:… read more 

January 22, 2018, Filed Under: Computer Hardware, Performance, Performance Counters

A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing)

A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing) Introduction: In December 2017, my colleague Damon McDougall (now at AMD) asked for help in porting the fused multiply-add example code from a Colfax report (https://colfaxresearch.com/skl-avx512/) to the Xeon Phi x200 (Knights Landing) processors here at TACC.   There was… read more 

December 6, 2016, Filed Under: Cache Coherence Implementations, Computer Architecture, Computer Hardware, Performance

Memory Latency on the Intel Xeon Phi x200 “Knights Landing” processor

The Xeon Phi x200 (Knights Landing) has a lot of modes of operation (selected at boot time), and the latency and bandwidth characteristics are slightly different for each mode. It is also important to remember that the latency can be different for each physical address, depending on the location of… read more 

  • Page 1
  • Page 2
  • Go to Next Page »

Primary Sidebar

Recent Posts

  • Single-core memory bandwidth: Latency, Bandwidth, and Concurrency
  • Dr. Bandwidth is moving on…
  • The evolution of single-core bandwidth in multicore systems — update
  • “Memory directories” in Intel processors
  • The evolution of single-core bandwidth in multicore processors

Tags

accelerated computing arithmetic cache communication configuration coprocessor Distributed cache DRAM Hash functions high performance computing Knights Landing memory bandwidth memory latency microprocessors MMIO MTRR Multicore processors Opteron STREAM benchmark synchronization TLB Virtual Memory Xeon Phi

UT Home | Emergency Information | Site Policies | Web Accessibility | Web Privacy | Adobe Reader

© The University of Texas at Austin 2025