UT Shield

Circuit Research Lab

University of Texas Austin

Circuit Research Lab

Patents

    1. S. V. Sreenivasan, P. Ajay, A. Sayal, M. Mcdermott, J. Kulkarni, “Nanofabrication and design techniques for 3D ICs and configurable ASICs” US patent application 17273713
    2. S. V. Sreenivasan, A. Mallavarapu, J. Kulkarni, M. Watts, S. Banerjee, “Catalyst influenced chemical etching for fabricating three-dimensional SRAM architectures and optical waveguides” US patent application 16872651
    3. A. Bonetti, J. P. Kulkarni, C. Tokunaga, M. Cho, P. Meinerzhagen, and M. Khellah, “Voltage level shifter monitor with tunable voltage level shifter replica circuit” filed USPTO 15/394, 296
    4. J. P. Kulkarni, V. De and M. Khellah, “Aging aware dynamic keeper apparatus and associated method”, filed USPTO 15/604519
    5. J. P. Kulkarni, and M. Khellah, “Low swing bitline for sensing arrays” filed USPTO, 15/485,059
    6. M. Cho, J. P. Kulkarni, C. Tokunaga, M. Khellah, and J. Tschanz “Adaptive voltage system for aging guard-band reduction” filed USPTO 15/477913
    7. M. Cho, J. P. Kulkarni, C. Tokunaga, M. Khellah, and J. Tschanz “Retention minimum voltage determination techniques”, US patent 10 , 199 , 091
    8. A. Thaploo, J. Kulkarni, B. Borole, A. Appu, A. Koker, K. Sinha, W. Fu, “System, apparatus and method for reducing voltage swing on an interconnect” US patent 10,762,877
    9. J. P. Kulkarni, Y. Shim, and P. Meinerzhagen, “Apparatus and method for reducing di/dt” US patent 11,079,830
    10. J. P. Kulkarni, Y. Shim, P. Meinerzhagen, M. Khellah “Bi-directional, multi-mode charge pump” US patent 10,511,224
    11. J. P. Kulkarni, I. Rajwani, and E. Donkoh, “Reduced swing bitline apparatus and method” US patent 9947, 388
    12. F. Sheikh, A. Sharma, and J. P. Kulkarni, “Fast Fourier transform architecture” US patent 10,713,333
    13. H. Bonakdar, J.P. Kulkarni, “Register files including distributed capacitor circuit blocks”, US Patent 9,767,858
    14. Y. Shim, J. P. Kulkarni, P. Meinerzhagen, and M. Khellah, “Apparatus and method for reducing di/dt during power wake-up”, US Patent 9,755,631
    15. J. P. Kulkarni, “Memory device including encoded data-line multiplexer” US Patent 9905,278
    16. J. P. Kulkarni, P. Kolar, A. Sharma, S. Chatterjee, K. Subramanian, F. Sheikh, W. H. Ma, “Capacitive wordline boosting” filed USPTO 14/752464
    17. J. P. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah, and T.-C. Hsueh “Digitally trimmable integrated resistors using resistive memory devices” US Patent 9,589,615
    18. A. Trivedi, J. P. Kulkarni, D. Somasekhar, M. Khellah, C. Tokunaga, J. Tschanz, “Current Steering Level Shifter” US Patent 9,385,722
    19. A. Trivedi, J. P. Kulkarni, C. Tokunaga, M. Khellah, , J. Tschanz, “Voltage level shifter” US Patent 9,621,163
    20. J. P. Kulkarni, A. Thaploo, I. Rajwani, K. Koo, E. Karl, M. Khellah, “Assist circuit for memory” US Patent 9,355,694
    21. J. P. Kulkarni, P. Meinerzhagen, D. Somasekhar, J. Tschanz, and V. De “Apparatus for charge recovery during low power mode” US Patent 9,948,179
    22. J. P. Kulkarni, B. Geuskens, J. Tschanz, V. De and M. Khellah “Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks” US Patent 9,633,716
    23. J. P. Kulkarni, K. Bowman, J. Tschanz and V. De “Resilient register file circuit for dynamic variation tolerance and method of operating the same”  US Patent 9,329,918
    24. J. Nasrullah, K. Kwan, J. P. Kulkarni and M. Khellah “Method and systems for energy efficiency and energy efficiency and energy conservation including entry and exit latency reduction for low power states”, US Patent 9,665,144  and PCT/US2012/066652
    25. I. Rajwani, S. Damaraju, N. Cooray, M. Khellah and J. P. Kulkarni “Memory array with extended write operation” filed USPTO/12642444
    26. P. Meinerzhagen, J. P. Kulkarni, M. Khellah, C. Dray, D. Somasekhar, J. Tschanz and V. De “Apparatus for dual purpose charge pump” US Patent 9,230,636
    27. J. P. Kulkarni, M. Khellah, J. Tschanz, B. Geuskens, and V. De “Apparatus for reducing write minimum supply voltage for memory” US patent 9,153,304
    28. A. Raychowdhury, J. P. Kulkarni, and J. Tschanz “Multi-supply sequential logic unit” US patent 8,901,819
    29. J. P. Kulkarni, D. Somasekhar “Low voltage swing repeater” US patent 8,847,633
    30. C. Wilkerson, A. Alameldeen, and J. P. Kulkarni, “Adaptive self-repairing cache” US patent 8,719,502
    31. J. P. Kulkarni, D. Somasekhar, J. Tschanz and V. De “Circuits and methods for memory” US patent 8488390 and PCT/US2012/032688
    32. J. P. Kulkarni, M. Khellah, B. Geuskens, A. Raychowdhury, T. Karnik and V. De “Memory write operation methods and circuits” US patent 8467263 and PCT/US2011/040458, 2011
    33. J. P. Kulkarni and K. Roy “Static random access memory cell and devices using the same”, US patent 7952912
    34. J. P. Kulkarni and K. Roy “Memory cell with built-in process variation tolerance” US patent 7672152

 

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