Intel provides nice schematic diagrams of the layouts of their processor chips, but provides no guidance on how the user-visible core numbers and L3 slice numbers map to the locations on the die. Most of the time there is no “need” to know the locations of the units, but there… read more
Computer Architecture
The Surprising Effectiveness of Non-Overlapping, Sensitivity-Based Performance Models
This was a keynote presentation at the “2nd International Workshop on Performance Modeling: Methods and Applications” (PMMA16), June 23, 2016, Frankfurt, Germany (in conjunction with ISC16). The presentation discusses a family of simple performance models that I developed over the last 20 years — originally in support of processor and… read more
Intel’s future “CLDEMOTE” instruction
I recently saw a reference to a future Intel “Atom” core called “Tremont” and ran across an interesting new instruction, “CLDEMOTE”, that will be supported in “Future Tremont and later” microarchitectures (ref: “Intel® Architecture Instruction Set Extensions and Future Features Programming Reference”, document 319433-035, October 2018). The “CLDEMOTE” instruction is… read more