• Skip to main content
  • Skip to primary sidebar
UT Shield
The University of Texas at Austin

Computer Architecture

January 9, 2019, Filed Under: Computer Architecture, Performance

New Year’s Updates

As part of my attempt to become organized in 2019, I found several draft blog entries that had never been completed and made public. This week I updated three of those posts — two really old ones (primarily of interest to computer architecture historians), and one from 2018: July 2012:… read more 

January 7, 2019, Filed Under: Cache Coherence Implementations, Cache Coherence Protocols, Computer Architecture, Linux, Performance Counters

SC18 paper: HPL and DGEMM performance variability on Intel Xeon Platinum 8160 processors

Here are the annotated slides from my SC18 presentation on Snoop Filter Conflicts that cause performance variability in HPL and DGEMM on the Xeon Platinum 8160 processor. This slide presentation includes data (not included in the paper) showing that Snoop Filter Conflicts occur in all Intel Scalable Processors (a.k.a., “Skylake… read more 

August 1, 2018, Filed Under: Computer Architecture, Computer Hardware, Performance

Why I hate MPI (from a performance analysis perspective)

According to Dr. Bandwidth, performance analysis has two recurring themes: How fast should this code (or “simple” variations on this code) run on this hardware? If I am analyzing (apparent) performance shortfalls, how can I distinguish between cause and effect? For very simple codes, it may be possible to do… read more 

  • « Go to Previous Page
  • Page 1
  • Page 2
  • Page 3
  • Page 4
  • Page 5
  • Page 6
  • Interim pages omitted …
  • Page 8
  • Go to Next Page »

Primary Sidebar

Recent Posts

  • Single-core memory bandwidth: Latency, Bandwidth, and Concurrency
  • Dr. Bandwidth is moving on…
  • The evolution of single-core bandwidth in multicore systems — update
  • “Memory directories” in Intel processors
  • The evolution of single-core bandwidth in multicore processors

Tags

accelerated computing arithmetic cache communication configuration coprocessor Distributed cache DRAM Hash functions high performance computing Knights Landing memory bandwidth memory latency microprocessors MMIO MTRR Multicore processors Opteron STREAM benchmark synchronization TLB Virtual Memory Xeon Phi

UT Home | Emergency Information | Site Policies | Web Accessibility | Web Privacy | Adobe Reader

© The University of Texas at Austin 2025