“Memory Bandwidth and System Balance in HPC Systems” If you are planning to attend the SuperComputing 2016 conference in Salt Lake City next month, be sure to reserve a spot on your calendar for my talk on Wednesday afternoon (4:15pm-5:00pm). I will be talking about the technology and market trends… read more
Computer Architecture
Counting Stall Cycles on the Intel Sandy Bridge Processor
Intuition might suggest that defining what a “stall cycle” is on a processor should be relatively straightforward. For some processors, this is actually the case — particularly in-order processors with a very small number of execution units and a very small number of non-pipelined instructions. For modern out-of-order processors, coming… read more
Memory Bandwidth on Xeon Phi (Knights Corner)
A Quick Note There are a lot of topics that could be addressed here, but this short note will focus on bandwidth from main memory (using the STREAM benchmark) as a function of the number of threads used. Published STREAM Bandwidth Results Official STREAM submission at: http://www.cs.virginia.edu/stream/stream_mail/2013/0015.html Compiled with icc… read more