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January 1, 2018, Filed Under: Cache Coherence Implementations, Cache Coherence Protocols, Computer Architecture, Computer Hardware, Reference

Notes on “non-temporal” (aka “streaming”) stores

Memory systems using caches have a lot more potential flexibility than most implementations are able to exploit – you get the standard behavior all the time, even if an alternative behavior would be allowable and desirable in a specific circumstance.  One area in which many vendors have provided an alternative… read more 

December 6, 2016, Filed Under: Cache Coherence Implementations, Computer Architecture, Computer Hardware, Performance

Memory Latency on the Intel Xeon Phi x200 “Knights Landing” processor

The Xeon Phi x200 (Knights Landing) has a lot of modes of operation (selected at boot time), and the latency and bandwidth characteristics are slightly different for each mode. It is also important to remember that the latency can be different for each physical address, depending on the location of… read more 

November 22, 2016, Filed Under: Computer Architecture, Computer Hardware

SC16 Invited Talk: Memory Bandwidth and System Balance in HPC Systems

I have been involved in HPC for over 30 years: 12 years as student & faculty user in ocean modeling, 12 years as a performance analyst and system architect at SGI, IBM, and AMD, and over 7 years as a research scientist at TACC. This history is based on my… read more 

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