Intuition might suggest that defining what a “stall cycle” is on a processor should be relatively straightforward. For some processors, this is actually the case — particularly in-order processors with a very small number of execution units and a very small number of non-pipelined instructions. For modern out-of-order processors, coming… read more
Memory Bandwidth on Xeon Phi (Knights Corner)
A Quick Note There are a lot of topics that could be addressed here, but this short note will focus on bandwidth from main memory (using the STREAM benchmark) as a function of the number of threads used. Published STREAM Bandwidth Results Official STREAM submission at: http://www.cs.virginia.edu/stream/stream_mail/2013/0015.html Compiled with icc… read more
Notes on the mystery of hardware cache performance counters
In response to a question on the PAPI mailing list, I scribbled some notes to try to help users understand the complexity of hardware performance counters for cache accesses and cache misses, and thought they might be helpful here…. For any interpretation of specific hardware performance counter events, it is… read more