As many of you know, the Texas Advanced Computing Center is in the midst of installing “Stampede” — a large supercomputer using both Intel Xeon E5 (“Sandy Bridge”) and Intel Xeon Phi (aka “MIC”, aka “Knights Corner”) processors. In his blog “The Perils of Parallel”, Greg Pfister commented on the… read more
high performance computing
Is “ordered summation” a hard problem to speed up?
Sometimes things that seem incredibly difficult aren’t really that bad…. I have been reviewing technology challenges for “exascale” computing and ran across an interesting comment in the 2008 “Technology Challenges in Achieving Exascale Systems” report. In Section 5.8 “Application Assessments”, Figure 5.16 on page 82 places “Ordered Summation” in the… read more
Opteron/PhenomII STREAM Bandwidth vs CPU and DRAM Frequency
In a recent post (link) I showed that local memory latency is weakly dependent on processor and DRAM frequency in a single-socket Phenom II system. Here are some preliminary results on memory bandwidth as a function of CPU frequency and DRAM frequency in the same system. This table does not… read more