I have been involved in HPC for over 30 years: 12 years as student & faculty user in ocean modeling, 12 years as a performance analyst and system architect at SGI, IBM, and AMD, and over 7 years as a research scientist at TACC. This history is based on my… read more
microprocessors
Intel discloses “vector+SIMD” instructions for future processors
The art and science of microprocessor architecture is a never-ending struggling to balance complexity, verifiability, usability, expressiveness, compactness, ease of encoding/decoding, energy consumption, backwards compatibility, forwards compatibility, and other factors. In recent years the trend has been to increase core-level performance by the use of SIMD vector instructions, and… read more
Notes on the mystery of hardware cache performance counters
In response to a question on the PAPI mailing list, I scribbled some notes to try to help users understand the complexity of hardware performance counters for cache accesses and cache misses, and thought they might be helpful here…. For any interpretation of specific hardware performance counter events, it is… read more