• Skip to main content
  • Skip to primary sidebar
UT Shield
The University of Texas at Austin

Archives for November 2010

November 8, 2010, Filed Under: Computer Hardware

Optimizing AMD Opteron Memory Bandwidth, Part 2: single-thread, read-only

In a previous entry, I started discussing the issues related to memory bandwidth for a read-only kernel on a sample AMD Opteron system. The naive implementation gave a performance of 3.393 GB/s when compiled at “-O1” (hereafter “Version 001”) and 4.145 GB/s when compiled at “-O2” (hereafter “Version 002”). Today… read more 

November 3, 2010, Filed Under: Computer Hardware

Optimizing AMD Opteron Memory Bandwidth, Part 1: single-thread, read-only

The first installment in a discussion of memory bandwidth in a very simple case — reading an array and summing the elements.

  • « Go to Previous Page
  • Page 1
  • Page 2

Primary Sidebar

Recent Posts

  • Single-core memory bandwidth: Latency, Bandwidth, and Concurrency
  • Dr. Bandwidth is moving on…
  • The evolution of single-core bandwidth in multicore systems — update
  • “Memory directories” in Intel processors
  • The evolution of single-core bandwidth in multicore processors

Tags

accelerated computing arithmetic cache communication configuration coprocessor Distributed cache DRAM Hash functions high performance computing Knights Landing memory bandwidth memory latency microprocessors MMIO MTRR Multicore processors Opteron STREAM benchmark synchronization TLB Virtual Memory Xeon Phi

UT Home | Emergency Information | Site Policies | Web Accessibility | Web Privacy | Adobe Reader

© The University of Texas at Austin 2025