In response to my previous blog entry, a question was asked about how to manage coherence for cached memory-mapped IO regions. Here are some more details… Maintaining Coherence with Cached Memory-Mapped IO For the “read-only” range, cached copies of MMIO lines will never be invalidated by external traffic, so repeated… read more
Computer Hardware
Notes on Cached Access to Memory-Mapped IO Regions
When attempting to build heterogeneous computers with “accelerators” or “coprocessors” on PCIe interfaces, one quickly runs into asymmetries between the data transfer capabilities of processors and IO devices. These asymmetries are often surprising — the tremendously complex processor is actually less capable of generating precisely controlled high-performance IO transactions than… read more
Some comments on the Xeon Phi coprocessor
As many of you know, the Texas Advanced Computing Center is in the midst of installing “Stampede” — a large supercomputer using both Intel Xeon E5 (“Sandy Bridge”) and Intel Xeon Phi (aka “MIC”, aka “Knights Corner”) processors. In his blog “The Perils of Parallel”, Greg Pfister commented on the… read more