In response to a question on the PAPI mailing list, I scribbled some notes to try to help users understand the complexity of hardware performance counters for cache accesses and cache misses, and thought they might be helpful here…. For any interpretation of specific hardware performance counter events, it is… read more
Computer Hardware
Coherence with Cached Memory-Mapped IO
In response to my previous blog entry, a question was asked about how to manage coherence for cached memory-mapped IO regions. Here are some more details… Maintaining Coherence with Cached Memory-Mapped IO For the “read-only” range, cached copies of MMIO lines will never be invalidated by external traffic, so repeated… read more
Notes on Cached Access to Memory-Mapped IO Regions
When attempting to build heterogeneous computers with “accelerators” or “coprocessors” on PCIe interfaces, one quickly runs into asymmetries between the data transfer capabilities of processors and IO devices. These asymmetries are often surprising — the tremendously complex processor is actually less capable of generating precisely controlled high-performance IO transactions than… read more