Defect rates and chip yields in the fabrication of complex semiconductor chips (like processors) are typically very tightly held secrets. In the current era of multicore processors even the definition of “yield” requires careful thinking — companies have adapted their designs to tolerate defects in single processor cores, allowing them… read more
Mapping addresses to L3/CHA slices in Intel processors
Starting with the Xeon E5 processors “Sandy Bridge EP” in 2012, all of Intel’s mainstream multicore server processors have included a distributed L3 cache with distributed coherence processing. The L3 cache is divided into “slices”, which are distributed around the chip — typically one “slice” for each processor core. Each… read more
Die Locations of Cores and L3 Slices for Intel Xeon Processors
Intel provides nice schematic diagrams of the layouts of their processor chips, but provides no guidance on how the user-visible core numbers and L3 slice numbers map to the locations on the die. Most of the time there is no “need” to know the locations of the units, but there… read more