UT Shield
Circuit Research Lab

Publications

2025

  1. Yixin Qin*, Saikat Chakraborty*, Zijian Zhao, Kijoon Kim, Suhwan Lim, Jongho Woo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Xiao Gong, Asif Khan, Vijaykrishnan Narayanan, Jaydeep P Kulkarni, and Kai Ni, “Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs with Gate-Side Injection”, IEEE Transactions on Electron Devices (TED), accepted, Invited paper for Special issue on IEDM 2024 (*= Equal Contributing Authors).
  2. Mengtian Yang, Yipeng Wang, Chieh-Pu Lo, Xiuhao Zhang, Sirish Oruganti and Jaydeep P. Kulkarni, “GSAcc: Accelerate 3D Gaussian Splatting via Depth Speculation and Gaussian-centric Rasterization”, 62nd ACM/IEEE Design Automation Conference (DAC), June 2025 (accepted)
  3. Yixin Qin*, Saikat Chakraborty*, Zijian Zhao, Sizhe Ma, Kijoon Kim, Suhwan Lim, Jongho Woo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni, and Kai Ni, “Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage”, IEEE International Reliability Physics Symposium (IRPS), March 30-April 3, 2025, Monterey, CA, USA (accepted) (*= Equally Contributing Authors).
  4. Sizhe Ma*, Saikat Chakraborty*, Yixin Qin, Zijian Zhao, Kijoon Kim, Suhwan Lim, Jongho Woo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni, and Kai Ni, “Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection”, IEEE International Reliability Physics Symposium (IRPS), March 30-April 3, 2025, Monterey, CA, USA (accepted), (*= Equally Contributing Authors)
  5. Meizhi Wang, Yi-Ru Chen, S. S. Teja Nibhanupudi, Elham Amini, Antonio Saaverdra, Yinan Wang, Daniel Wasserman, Jean-Pierre Seifert, Jaydeep Kulkarni, “Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology” International  Symposium on Physical Design (ISPD) 2025 (accepted)
  6. Raman Sundara Raman, Lizy John, and Jaydeep P. Kulkarni, “SPARK : Sparsity and reuse-aware, energy-efficient, reconfigurable near-cache architecture for Integer Linear Programming Acceleration”, 2025 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025 (accepted)

2024

  1. Yixin Qin*, Saikat Chakraborty*, Zijian Zhao, Kijoon Kim, Suhwan Lim, Jongho Woo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Xiao Gong, Asif Khan, Vijaykrishnan Narayanan, Jaydeep P Kulkarni, and Kai Ni, “Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping”, International Electron Devices Meeting (IEDM), December 2024 (Accepted)  (*= Equally Contributing Authors)
  2. Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, and Jaydeep P. Kulkarni. “Invited paper: CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems.” IEEE Asian Solid State Circuits Conference (ASSCC), November 2024 (Invited)
  3. Juhan Ahn, Saroj Satapathy, Jaydeep P. Kulkarni, “Optimization of Complementary Reconfigurable Field-Effect Transistor for Improved Circuit-Level Metrics”, IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2024, (accepted)
  4. Chieh-Pu Lo, Sirish Oruganti, Yipeng Wang, Mengtian Yang, Shanshan Xie, Jaydeep P. Kulkarni, “Data Movement-Aware, Ping-Pong Ising Machine Supporting Full Connectivity and Variable Bitwidths”, IEEE European Solid-State Electronics Research Conference (ESSERC), September 2024 (accepted)
  5. Saikat Chakraborty and Jaydeep P. Kulkarni, “Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications”, 2024 Device Research Conference (DRC), June 2024, (accepted)
  6. Juhan Ahn, Saroj Satapathy, and Jaydeep P. Kulkarni, “Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers” IEEE Device Research Conference (DRC), June 2024, (accepted)
  7. Siddartha Raman, Lizy John, Jaydeep P. Kulkarni, “NEM-GNN – DAC/ADC-less, scalable, reconfigurable, graph and sparsity-aware near-memory accelerator for graph neural networks” ACM Transactions on Architecture and Code Optimization (TACO), (accepted)
  8. S. S. Teja Nibhanupudi, Anupam Roy, Dmitry Veksler, Matthew Coupin, Kevin C. Matthews, Matthew Disiena, Ansh, Jatin V Singh, Ioana R Gearba-Dolocan, Jamie Warner, Jaydeep P. Kulkarni, Gennadi Bersuker, Sanjay K. Banerjee, “Ultra-fast switching memristors based on two-dimensional materials”, Nature Communications, 15, 2334 (2024), DOI: 10.1038/s41467-024-46372-y
  9. Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni. “CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems.” IEEE Custom Integrated Circuits Conference (CICC), April 2024, (accepted)
  10. Saikat Chakraborty, Jaydeep P. Kulkarni, “Comprehensive TCAD-based Retention Study of Thyristor RAM (TRAM) for Low-Power and High-Speed Cryogenic Memory Applications” IEEE Transactions on Electron Devices (TED), (accepted)
  11. Sumanth N Karanth, Sirish Oruganti, Meizhi Wang and Jaydeep P Kulkarni et al., “Randomization approaches for Secure SAR ADC design resilient against Power Side-Channel Attacks” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May, 2024 (accepted)
  12. Siddhartha Raman Sundara Raman, Lizy John, and Jaydeep P. Kulkarni, “SACHI: A Stationarity-Aware, All-Digital, Near-Cache, Ising Architecture” International Symposium on High-Performance Computer Architecture, (HPCA), March 2024, accepted
  13. Sirish Oruganti*, Meizhi Wang*, Vishnuvardhan V. Iyer, Raghavan Kumar, Sanu K. Mathew, Yipeng Wang, Mengtian Yang, Jaydeep P. Kulkarni. “Power and EM Side Channel Attack resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation based on Tunable Replica Circuits” IEEE International Solid-State Circuits Conference (ISSCC),  February 2024 (accepted)
  14. Yipeng Wang, Mengtian Yang, Chieh-pu Lo., Jaydeep P. Kulkarni. “Vecim: A 289.13GOPS/W RISC-V Vector Co-processor with Compute-in-memory Vector Register File for Efficient High-performance Computing” IEEE International Solid-State Circuits Conference (ISSCC), February 2024 [Slides]

2023

  1. Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, and Jaydeep P. Kulkarni, “eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design with Embedded Dynamic Random-Access Memory Array Realizing Adaptive Data Converters” IEEE Journal of Solid-State Circuits (JSSC), accepted
  2. Mengtian Yang*, Yipeng Wang*, and Jaydeep P. Kulkarni, “A 118 GOPS/mm^2 3D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication” IEEE International Conference on High Performance Computing, Data, and Analytics  (HiPC), December 2023, (accepted)
  3. Sumanth N Karanth, Sirish Oruganti, Meizhi Wang and Jaydeep P Kulkarni, “RI-SAR: Randomized Input SAR ADC Resilient to Power Side Channel Attacks”, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), October, 2023 (accepted)
  4. Naman Maheshwari, Nicholas Malaya, Scott Moe, Jaydeep P. Kulkarni, Sudhanva Gurumurthi, “An Estimator for the Sensitivity to Perturbations of Deep Neural Networks” arXiv:2307.12679v1 [Paper]
  5. Rishabh Sehgal, Rishab Mehra, Can Ni and Jaydeep P. Kulkarni, “Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines” IEEE 49th European Solid-State Circuits Conference (ESSCIRC), September  2023 (accepted)
  6. Yipeng Wang, Mengtian Yang, Shanshan Xie, Meizhi Wang, Jaydeep P Kulkarni “CIMGN: an Energy-Efficient All-Digital Compute-in-Memory Graph Neural Network Processor” IEEE 49th European Solid-State Circuits Conference (ESSCIRC), September  2023 (accepted)
  7. S.S. Teja Nibhanupudi, Sirish Oruganti, Rahul Mathur, Nishant Gupta, Meizhi Wang, and Jaydeep P. Kulkarni, “Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges”, 60th ACM/IEEE Design Automation Conference (DAC), July 2023 (Invited paper)
  8. Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep Kulkarni, Lizy K. John, “CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration” IEEE Transactions on Reconfigurable Technology and Systems (TRETS)
  9. Sirish Oruganti, Nishant Gupta, Sai Subrahmanya Teja Nibhanupudi, Meizhi Wang, Jaydeep Kulkarni, “Security Robustness of Buried Power Rail Interconnect Technology: Modeling, Analysis and Countermeasures” IEEE 73rd Electronic Components and Technology Conference (ECTC), May 2023
  10. Yipeng Wang, Shanshan Xie, Jacob Rohan, Meizhi Wang, Mengtian Yang, Sirish Oruganti, Jaydeep P Kulkarni. “A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAM enabled Search-reduce.” IEEE Custom Integrated Circuits Conference (CICC),  April 2023
  11. Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, and Nan Sun, “An In-Memory-Computing Charge-Domain Ternary CNN Classifier”; IEEE Journal of Solid State Circuits (JSSC) (accepted)
  12. Rishabh Sehgal, Tanmay Thareja, Shanshan Xie, Can Ni, Jaydeep P. Kulkarni, “A Bit-Serial, Compute in SRAM Design featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy Efficient DNN Inference”; IEEE Journal of Solid State circuits (JSSC) (accepted)
  13. Stafford Hutchins, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, and Jaydeep P. Kulkarni, “High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology” IEEE Solid State Circuit Letters (SSCL) (accepted)
  14. Shanshan Xie, Mengtian Yang, S. Andrew Lanham, Meizhi Wang, Yipeng Wang, Sirish Oruganti, and Jaydeep P Kulkarni,  “Snap-SAT: A One-Shot, Energy-Performance-Aware, All-Digital, Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems.” IEEE International Solid-State Circuits Conference (ISSCC),  February 2023, [Paper] [Slides]

2022

  1. Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Daniel Smith, Daniel Fisher, Norman Robson, Brian Cline, and Jaydeep. P. Kulkarni, “Early Design/Technology Exploration of BEOL Options for Hybrid Wafer Bonded Split-SRAM”, IEEE Transactions on Electron Devices (TED), vol. 69, no. 12, pp. 6731-6737, Dec. 2022
  2. Siddhartha Raman Sundara Raman, Shanshan Xie, and Jaydeep P. Kulkarni, “IGZO CIM: Computing ternary neural network using multi-level Capacitorless Indium Gallium Zinc Oxide based eDRAM” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) (accepted)
  3. Meizhi Wang*, Sirish Oruganti*, Shanshan Xie, Raghavan Kumar, Sanu Mathew, and Jaydeep P. Kulkarni, “Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 529-532,  September 2022  (*=Equally contributed authors)
  4. Shanshan Xie, Siddhartha Raman, Can Ni, Meizhi Wang, Mengtian Yang, and Jaydeep P. Kulkarni, “Ising-CIM: A Reconfigurable and Scalable Compute within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems”’ IEEE Journal of Solid State Circuits (JSSC),  vol. 57, no. 11, pp. 3453-3465, Nov. 2022, [Paper]
  5. S. S. Teja Nibhanupudi, Divya Prasad, Shidhartha Das, Odysseas Zografos, Bilal Chehab, Satadru Sarkar,  Alex Robinson, Anshul Gupta, Alessio Spessot, Peter Debacker, Diederik Verkest, Julien Ryckaert, Geert Hellings, James Myers, Brian Cline, and Jaydeep P. Kulkarni, “A Holistic Evaluation of Buried Power Rails and Back-side Power Grids for sub-5nm CMOS technology nodes” IEEE Transactions on Electron Devices (TED), IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4453-4459, Aug. 2022
  6. Jacob N. Rohan, and Jaydeep P. Kulkarni, “Systolic-RAM: Scalable Direct Convolution Using In-Memory Data Movement” IEEE Solid-State Circuits Letters (SSCL),  Invited paper for the special issue on ASSCC 2021, [Paper]
  7. Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, and Jaydeep P. Kulkarni, “Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Compact Schmitt Trigger ADCs” IEEE VLSI Circuit Symposium (VLSI Symposium), June 2022, [Paper]
  8. Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad H. Hasan, Uddalak Bhattacharya, Eric Karl, and Jaydeep P. Kulkarni, “A high Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programable Metal eFuse on Intel4 Logic Technology”, IEEE VLSI Circuit Symposium (VLSI Symposium), June 2022, [Paper]
  9. Saikat Chakraborty and Jaydeep P. Kulkarni, “Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM” IEEE Device Research Conference (DRC), June 2022
  10. Saikat Chakraborty and Jaydeep P. Kulkarni, “Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing” IEEE Device Research Conference (DRC), June 2022
  11. Rishab Mehra, S.S Teja Nibhanupudi, and Jaydeep P. Kulkarni, “Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation” IEEE Device Research Conference (DRC), June 2022
  12. S. S. Teja Nibhanupudi, Dmitry Veksler, Anupam Roy, Matthew Coupin, Kevin Matthews, Jamie Warner, Gennadi Bersuker, Jaydeep P. Kulkarni, and Sanjay K. Banerjee “Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices”, IEEE Device Research Conference (DRC), June 2022
  13. Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, and Jaydeep P. Kulkarni, “Enabling In-Memory Computations in Non-Volatile SRAM Designs”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), May 2022, [Paper]
  14. Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep Kulkarni, and Lizy K. John, “CoMeFa: Compute-in-Memory Blocks for FPGAs” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2022, Best student paper award, [Paper]
  15. Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep Kulkarni, and Tony Tae-Hyoung Kim, “An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS),  Accepted May 2022, [Paper]
  16. Christopher H. Bennett*, Jacob N. Rohan*, T. Xiao, I. Wilcox, B. Feinberg, G. Ng, R. Jacobs-Gedrim, J. Black, D. Black, D. Hughart, J. Kulkarni, and M. Marinella, “Implications of Dose-Rate events on Spin-Transfer-Torque and Spin-Orbit-Torque Memory Bit Cell Designs” Journal of Radiation Effects, Research and Engineering (JRERE), April 2022 (*= Equally contributed Authors)
  17. Jacob Rohan, Parth Shroff,  and Jaydeep P. Kulkarni, “Machine Learning Techniques for Improved Non-Ideal Non-Volatile Memory Modeling” Government Microelectronic Conference (GOMACTech),  March 2022
  18. Rahul Mathur, Mudit Bhargava, Brian Cline, Shairfe Salahuddin, Anshul Gupta, Pieter Schuddinck, Julien Ryckaert, and Jaydeep P. Kulkarni, “Buried Interconnects for sub-5nm SRAM Design”, IEEE Transactions on Electron Devices (TED), January 2022, [Paper]
  19. Kelly Liang, Xin Xu, Yuchen Zhou, Xao Wang, Calla M. McCulley, Liang Wang, Jaydeep Kulkarni, and Ananth Dodabalapur, “Nanospike electrodes and charge nanoribbons: A new design for nanoscale thin-film transistors” Science advances AAAS (Science), pp. 1-5, Vol 8, Issue 4, 28 Jan 2022 [Paper]

2021

  1. Vishnuvardhan Iyer, Meizhi Wang, Jaydeep Kulkarni, and Ali Yilmaz, “A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations” IEEE International Conference on Intelligence and Security Informatics (ISI), November 2021, [Paper] 
  2. S. S. Teja Nibhanupudi*, Siddhartha Raman Sundara Raman*, Mikaël Cassé, Louis Hutin, and Jaydeep P. Kulkarni, “Ultra Low Voltage, UTBB-SOI Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) (accepted) (*=Equally contributed authors) [Paper] 
  3. Jacob N. Rohan, and Jaydeep P. Kulkarni, “Realizing Direct Convolution in Memory with Systolic-RAM”, IEEE Asian Solid State Circuits Conference (ASSCC), November 2021 [Paper] 
  4. Siddhartha Raman Sundara Raman, S.S Teja Nibhanupudi, Atanu. K. Saha, Sumeet Gupta, and Jaydeep P. Kulkarni, “Threshold Selector and Capacitive Coupled Assist Techniques for Write Voltage Reduction in Metal- Ferroelectric-Metal Field Effect Transistor” IEEE Transactions on Electron Devices (TED),  November 2021  [Paper] 
  5. Rahul Mathur, Ajay Krishna Ananda Kumar, Lizy John, and Jaydeep P. Kulkarni, “Thermal-Aware Design Space Exploration of 3D Systolic ML Accelerators” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), vol. 7, no. 1, pp. 70-78, June 2021, doi: 10.1109/JXCDC.2021.3092436  [Paper]
  6. Kelly Liang, Xiao Wang, Yuchen Zhao, Calla McCulley, Liang Wang, Jaydeep P. Kulkarni, and Ananth Dodabalapur, “Field-Emission Enhanced Contacts for Disordered Semiconductor based Thin-Film Transistors” IEEE Device Research Conference (DRC), June 2021  [Paper]
  7. Rishabh Sehgal, and Jaydeep P. Kulkarni, “Trends in Analog and Digital Intensive Compute-in-SRAM Designs” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS), June 2021, [Paper]
  8. Siddhartha Raman Sundara Raman, Shanshan Xie, and Jaydeep P. Kulkarni “Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors” Special session on Analog Computing, SoC, and Processing-in-Memory for AI Hardware, IEEE International Symposium on Circuits & Systems, (ISCAS), May 2021, DOI: 10.1109/ISCAS51556.2021.9401798 [Paper]
  9. S. S. Teja Nibhanupudi, Siddhartha Raman Sundara Raman, and Jaydeep P. Kulkarni, “Phase Transition Material assisted Low Power SRAM Design” IEEE Transactions on Electron Devices (TED), pp. 2281-2288, vol. 68, Issue 5, May 2021, DOI: 10.1109/TED.2021.3067849 [Paper]
  10. Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, and Jaydeep P. Kulkarni. “Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management” in IEEE Custom Integrated Circuits Conference (CICC), April 2021, [Paper] [Slides]
  11. Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, and Jaydeep P. Kulkarni, “Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks”, in IEEE Custom Integrated Circuits Conference (CICC), April 2021, [Paper] [Slides]
  12. Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, and Jaydeep P. Kulkarni, “3D-Split SRAM: Enabling Generational Gains in Advanced CMOS” in IEEE Custom Integrated Circuits Conference (CICC), April 2021 [Paper] [Slides]
  13. Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun, “An In-Memory-Computing Charge-Domain Ternary CNN Classifier” in IEEE Custom Integrated Circuits Conference (CICC), April 2021,  [Paper] [Slides] (Best student paper candidate)
  14. Rahul Mathur, Senthil Annamalai, Mudit Bhargava, Brian Cline, Jaydeep P. Kulkarni, “Buried Signal Explorations for sub-5nm SRAM Design” Synopsys User Group (SNUG) World 2021, April 2021 (Top Ten Presentation Award)
  15. Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, and Jaydeep P. Kulkarni “eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded Dynamic Memory Array Realizing Adaptive Data Converters and Charge Domain Computing” IEEE International Solid State Circuits Conference (ISSCC), pp. 248-249, February 2021, [Paper] [Slides]
  16. Siddhartha Raman Sundara Raman, Feng Wen, Ravi Pillarisetty, Vivek De, and Jaydeep P. Kulkarni, “High Noise Margin, Digital Logic Design using Josephson Junction Field-effect Transistors for Cryogenic Computing” IEEE Transaction on Applied Superconductivity (TAS), special issue on Applied Superconductivity Conference, January 2021, [Paper]

2020

  1. A. Sayal, S. Fathima, S. S. Teja Nibhanupudi, and J. P. Kulkarni, “COMPAC: Compressed Time Domain, Pooling Aware Convolution CNN Engine with Reduced Data Movement for Energy-Efficient AI Computing”, in IEEE Journal of Solid State Circuits (JSSC), Dec. 2020 [Paper]
  2. R. Mathur, M. Bhargava, S. Salahuddin, P. Schuddinck, J. Ryckaert, S. Annamalai, A. Gupta, Y. K. Chong, S. Sinha, B. Cline and J. P. Kulkarni, “Buried Bitline for sub-5nm SRAM Design” IEEE International Electron Device Meeting (IEDM), 2020 [Paper]
  3. J. P. Kulkarni, A. Malavasi, C. Augustine, C. Tokunaga, J. Tschanz, M. M. Khellah, V. De, “Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-bitcell SRAM in 10nm FinFET CMOS” IEEE VLSI Circuit Symposium (VLSI Symposium), June 2020 [Paper] [Slides]
  4. A. Sayal, P. Ajay, M. W. McDermott, S. V. Sreenivasan and J. P. Kulkarni, “M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  vol. 39, no. 12, pp. 4760-4776, Dec. 2020 [Paper]
  5. R. Mathur, X. Xu, A. Chao, P. Chandupatla, S. Hung, N. Tadepalli, S. Sinha, and J. Kulkarni, “Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology”, 70th IEEE Electronic Components and Technology Conference (ECTC), June 2020 [Paper]
  6. J. P. Kulkarni, A. Sayal, S. S. Teja Nibhanupudi, and S. Fatima, “All-Digital Time-Domain CNN engine using Bi-directional Memory Delay Lines” Government Microelectronic Conference (GOMACTech), March 2020
  7. J. P. Kulkarni, and S. S. Teja Nibhanupudi, “Non-volatile SRAM leveraging novel materials” Government Microelectronic Conference (GOMACTech), March 2020
  8. J. N. Rohan, P. Zhuang, S. S. Teja Nibhanupudi, S. K. Banerjee, and J. P. Kulkarni, “Machine Learning Assisted Compact Modeling of Cycle-to-cycle Variations in 2-D h-BN based RRAM devices” Government Microelectronic Conference (GOMACTech), March 2020
  9. A. Sayal, S. S. Teja Nibhanupudi, S. Fathima, and J. P. Kulkarni, “A 12.08 TOPS/W All-Digital Time-Domain CNN engine using Bi-directional Memory Delay Lines for Energy Efficient Edge Computing”, IEEE Journal of Solid-State Circuits (JSSC), pp. 60-75, Vol. 55, No. 1, January 2020, Invited Paper to Special issue on ISSCC 2019  [Paper]

2019

  1. D. Prasad, S. S. Teja Nibhanupudi, S. Das, O. Zografos, B. Chehab, S. Sarkar, R. Baert, A. Robinson, A. Spessot, P. Debacker, D. Verkest, J. Kulkarni, B. Cline, and S. Sinha, “Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm” IEEE International Electron Devices Meeting (IEDM), December 2019, pp. 446-449 [Paper]
  2. J. Rohan, P. Zhuang, S. S T. Nibhanupudi, S. K. Banerjee, J. P. Kulkarni “Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D h-BN based RRAM Devices” 77th Device Research Conference (DRC), June 2019 [Paper]
  3. S. Teja,  and J. P. Kulkarni, “High density NV-SRAM using memristor and selector as technology assist”, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), April  2019 (Best student paper candidate) [Paper]
  4. J. P. Kulkarni, and S. Teja, “Radiation Hardened Memory and Logic Design using Phase Transition Material’ Government Microelectronic Conference (GOMACTech), March 2019
  5. J. P. Kulkarni, A. Sayal, P. Ajay, M. McDermott, and S. V. Sreenivasan; “A Design Methodology for High-Mix, Low-Volume, Heterogeneously Integrated ASICs” Government Microelectronic Conference (GOMACTech), March 2019
  6. A. Sayal, S. Fathima, S.S. Teja Nibhanupudi and J. P. Kulkarni, “All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing” IEEE international Solid-State Circuits Conference (ISSCC), 2019, pp. 228-230 [Paper] [Slides]
  7. P. Meinerzhagen, C. Tokunaga, A. Malavasi, V. Vaidya, A. Mendon, D. Mathaikutty, J. Kulkarni, C. Augustine, M. Cho, S. Kim, G. Matthew, R. Jain, J. Ryan, C.-C. Peng, S. Paul, S. Vangal, B. P. Esparza, L. Cuellar, M. Woodman, B. Iyer, S. Maiyuran, G. Chinya, X. Zou, Y. Liao, K. Ravichandran, H. Wong, M. Khellah, J. Tschanz, and V. De, “An Energy-Efficient Graphics Processor in 14nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and VMIN Optimization” IEEE Journal of Solid State Circuits (JSSC) Special issue on ISSCC 2018, pp. 144-157, Vol. 54, No. 1, January 2019 [Paper]

2018

  1. S. Teja, A. Rai, A. Roy, S. K. Banerjee and J. P. Kulkarni, “Memory and Logic soft error improvement using phase transition material assisted transistors” IEEE International Conference on Emerging Electronics (ICEE), Bangalore, December 2018  [Paper]
  2. S. Motaman, S. Ghosh, and J. Kulkarni, “VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting” IEEE Transactions on Circuits and Systems-I (TCAS-I), pp. 1919-1928, Vol. 65, issue-6, June 2018 [Paper]
  3. S. Teja, and J.P. Kulkarni, “Soft-FET: Phase transition material assisted Soft switching Field Effect Transistor for supply voltage droop mitigation” 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, 2018, pp. 1-6. [Paper]
  4. S. Teja, and J.P. Kulkarni, “Phase Transition Material assisted circuits for improved soft error tolerance” Silicon Errors in Logic – System Effects Workshop (SELSE), March 2018
  5. P. Meinerzhagen, C. Tokunaga, A. Malavasi, V. Vaidya, A. Mendon, D. Mathaikutty, J. Kulkarni, C. Augustine, M. Cho, S. Kim, G. Matthew, R. Jain, J. Ryan, C.-C. Peng, S. Paul, S. Vangal, B. P. Esparza, L. Cuellar, M. Woodman, B. Iyer, S. Maiyuran, G. Chinya, X. Zou, Y. Liao, K. Ravichandran, H. Wong, M. Khellah, J. Tschanz, and V. De, “An Energy-Efficient Graphics Processor in 14nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and VMIN Optimization” International Solid State Circuits Conference (ISSCC), pp. 38-39, February 2018 [Paper]

2017 and Earlier

  1. S. Motaman, S. Ghosh, and J. Kulkarni; “Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing” ACM Journal on Emerging Technologies in Computing Systems (JETC), pp. 1-17, Vol. 14, issue-1, October 2017 [Paper]
  2. J. P. Kulkarni, C. Tokunaga, M. Cho, M. M. Khellah, J. W. Tschanz, and V. K. De “FMAX / VMIN and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS” VLSI Circuit Symposium (VLSI Symposium), pp. 116-117, June 2017 [Paper]
  3. J. P. Kulkarni, C. Tokunaga, C. Augustine, M. Khellah, J. Tschanz and V. De, “Adaptive and resilient high-performance memory design for dynamic variation tolerance” VLSI Test Symposium (VTS), April 2017 (Invited paper)
  4. J. P. Kulkarni, J. Keane, K.-H Koo, S. Nalam, Z. Guo, E. Karl, and K. Zhang, “5.6Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology” IEEE Journal of Solid State Circuits (JSSC) (special issue on ISSCC 2016), pp. 229-239, Vol. 52, No. 1, January 2017 [Paper]
  5. M. Cho, S. Kim, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De, “Post-Silicon Voltage Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating”, IEEE Journal of Solid State Circuits (JSSC), (special issue on ISSCC 2016), pp. 50 – 63, Vol. 52, No. 1, January 2017 [Paper]
  6. S. Srinivasa, A. Aziz, N. Shukla, X. Li, J. Sampson, S. Datta, J. P. Kulkarni, V. Narayanan, and S. Gupta, “Correlated Material Enhanced SRAMs with Robust Low Power Operation” IEEE Transactions on Electron Devices (TED), pp. 4744- 4752 Vol. 63, No. 12, December 2016 [Paper]
  7. A. Sharma, A. A. Goud, J. P. Kulkarni, and K. Roy, “Source-underlapped GaSb-InAs TFETs with applications to Gain Cell Embedded DRAMs” IEEE Transactions on Electron Devices (TED), pp. 2563-2569, Vol 63, No. 6, June 2016  [Paper]
  8. J. Keane, J. Kulkarni, K.-H Koo, S. Nalam, Z. Guo, E. Karl, and K. Zhang, “5.6Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology” International Solid State Circuits Conference (ISSCC), pp. 308-309, Feb. 2016 [Paper]
  9. M. Cho, S. Kim, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De, “Post-Silicon Voltage Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating” International Solid State Circuits Conference (ISSCC) pp. 152-153, February 2016 [Paper]
  10. J. P. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen Jr, C. Augustine, J. Tschanz, V. De, “A 409 GOPS/W Adaptive & Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin & Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature & Aging, IEEE Journal of Solid State Circuits (JSSC), pp. 117-129, Vol. 51, No. 1, January 2016 Special issue on ISSCC 2015 [Paper]
  11. S. Kim, Y.-C. Shih, K. Mazumdar, R. Jain, J. Ryan, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, and V. De, “Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator” IEEE Journal of Solid State Circuits (JSSC), pp. 18-30, Vol. 51, No. 1, January 2016 Special issue on ISSCC 2015 [Paper]
  12. S. Motaman, S. Ghosh, and J. Kulkarni, “A Novel Slope Detection Technique for Robust STTRAM Sensing” International Symposium on Low Power Electronics Design, (ISLPED), pp. 7-12, July 2015
  13. J. P. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen Jr, C. Augustine, J. Tschanz, V. De, “A 409 GOPS/W Adaptive & Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin & Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature & Aging” International Solid State Circuits Conference (ISSCC), pp. 82-83, February 2015 [Paper]
  14. S. Kim, Y.-C. Shih, K. Mazumdar, R. Jain, J. Ryan, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, and V. De, “Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally-Controlled Hybrid LDO/Switched-Capacitor VR with Fast Droop Mitigation” International Solid State Circuits Conference (ISSCC), pp. 154-155, February 2015
  15. R. Jain, B. Geuskens, M. Khellah, S. Kim, J. Kulkarni, J. Tschanz and V. De, “A 0.45-1V Fully Reconfigurable Switched Capacitor step down DC-DC converter with High Density MIM Capacitor in 22nm Tri-gate CMOS” IEEE Journal of Solid State Circuits (JSSC), pp. 1-11, vol. 49, No. 4, April 2014
  16. R. Pandey, V. Saripalli, J. P. Kulkarni, S. Datta, “Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability”, IEEE Electron Device Letters (EDL), pp. 393-395, Vol 35, No. 3, March 2014
  17. C. Tokunaga, J. Ryan, C. Augustine, J. Kulkarni, Y. Shih, S. Kim, R. Jain, K. Bowman, A. Raychowdhury, M. Khellah, J. Tschanz, V. De, “A 22nm Graphics Execution Core with Wide Voltage Range and 40% Higher Peak GFLOPS/W via Adaptive Clocking, Selective Boosting, and State-Retentive Sleep” International Solid State Circuits Conference (ISSCC), pp. 108-109, February 2014
  18. S. Gupta, J.P. Kulkarni, and K. Roy, “Tri-Mode Independent Gate FinFET based SRAM with Pass Gate Feedback: Technology-Circuit Co-design for Enhanced Cell Stability”, IEEE Transactions on Electron Devices (TED), pp. 3696-3704, vol. 60, No. 11, November 2013
  19. A. R. Alameldeen, N.S. Kim, S. M. Khan, H. R. Ghasemi, C. Wilkerson, J. Kulkarni, D. A. Jimenez, “Improving memory reliability power and performance using mixed cell designs” Intel Technology Journal (ITJ), pp. 36-53, vol. 17, issue 1, 2013
  20. J.P. Kulkarni, M. Khellah, J. Tschanz, B. Geuskens, R. Jain, S. Kim and V. De, “Dual-Vcc 8T-bitcell SRAM Array in 22nm Tri-gate CMOS for energy efficient operation across wide dynamic voltage range” VLSI Circuit Symposium (VLSI Symposium), pp. C126-C127, June 2013, (Conference highlight paper) [Paper]
  21. R. Jain, B. Geuskens, M. Khellah, S. Kim, J. Kulkarni, J. Tschanz and V. De, “A 0.45-1V Fully Reconfigurable Switched Capacitor step down DC-DC converter with High Density MIM Capacitor in 22nm Tri-gate CMOS” VLSI Circuit Symposium (VLSI Symposium), pp. C174-C175, June 2013 (Conference highlight paper)
  22. S. M. Khan, A. R. Alameldeen, C. Wilkerson, J. Kulkarni, D. A. Jimenez, “Improving Multi-Core Performance Using Mixed-Cell Cache Architecture”, International Symposium on High Performance Computer Architecture (HPCA), pp. 229-230, February 2013
  23. S. Gupta, J.P. Kulkarni, S. Datta and K. Roy, “Process-Variation Tolerant Heterojunction Intra-band Tunnel (HIBT) FETs for Low Voltage SRAMs”, IEEE Transactions on Electron Devices (TED), pp. 3533-3542, vol. 59, No. 12, December 2012
  24. S. Gupta, J.P. Kulkarni, S. Datta and K. Roy, “Dopant Straggle-free Heterojunction Intra-band Tunneling (HIBT) FETs with Abrupt Source/Drain Junctions, Low Drain-induced Barrier Lowering/Thinning and Reduced Variation in OFF current” 2012 Device Research Conference (DRC), June 2012
  25. M. Nicolaidis, L. Anghel, N. Zergainoh, Y. Zorian T. Karnik, J. Tschanz, J. Kulkarni, K. Bowman, M. Khellah, A. Raychowdhury, C. Tokunaga, S-L Lu, and V. De, “Designing Reliable Processor Cores” Design Automation and Test in Europe (DATE), March 2012 (invited paper)
  26. J. Kulkarni, B. Geuskens, T. Karnik, M. Khellah, J. Tschanz and V. De, “Capacitive-Coupling Wordline Boosting with Self-Induced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM” International Solid State Circuits Conference (ISSCC), pp. 234-235, February 2012 [Paper]
  27. J. P. Kulkarni and K. Roy, “Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design” IEEE Transactions on VLSI systems (TVLSI), pp. 319-332, vol. 20, No. 2, February 2012 (2015 IEEE TVLSI best paper award, Top-25 most downloaded TVLSI manuscript for the year 2012) [Paper]
  28. J. P. Kulkarni, A. Goel, P. Ndai and K. Roy, “Read-Disturb-Free, Differential Sensing 1R/1W Port 8T Bitcell Array” IEEE Transactions on VLSI systems (TVLSI), pp. 1727-1730, Vol. 19, Issue: 9, September 2011 [Paper]
  29. V. Saripalli, S. Datta, V. Narayanan, and J.P. Kulkarni, “Variation-Tolerant Ultra low-power Hetero-junction Tunnel FET SRAM Design” 7th International Symposium on Nanoscale Architectures (NANOARCH), pp. 45-52, June 2011
  30. B. Geuskens, M. Khellah, J. Kulkarni, T. Karnik and V. De “Opportunities for PMOS Read and Write Ports in Low Voltage Dual-Port 8T Bit-Cell Arrays” Custom Integrated Circuits Conference (CICC), pp. 1-4, September 2010
  31. M. Meterelliyoz, P. Song, F. Stellari, J. P. Kulkarni and K. Roy, “Characterization of Random Process Variations using Ultra Low Power High Sensitivity, Bias Free Sub-threshold Process Sensor” IEEE Transactions on Circuits and Systems-I (TCAS-I), pp. 1838-1847, Vol. 57, Issue:8, August 2010
  32. J. P. Kulkarni, C. Augustine, B. Jung and K. Roy, “Nano-Spiral Inductors for Low Power Digital Spintronic Circuits” IEEE Transactions on Magnetics (TMAG), pp. 1898-1901, vol. 46, No. 6, June 2010 [Paper]
  33. A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S.-L. Lu, V. De and M. Khellah, “PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction” International Solid State Circuits Conference (ISSCC), pp. 352-353, February 2010
  34. M. Meterelliyoz, A. Goel, J. P. Kulkarni and K. Roy, “Accurate Characterization of Random Process Variations Using a Robust Low-Voltage High-Sensitivity Sensor Featuring Replica-Bias Circuit” International Solid State Circuits Conference (ISSCC), pp. 186-187, February 2010
  35. J. Tschanz, K. Bowman, M. Khellah, C. Wilkerson, B. Geuskens, D. Somasekhar, A. Raychowdhury, J. Kulkarni, C. Tokunaga, S.-L. Lu, T. Karnik, V. De, “Resilient Design in Scaled CMOS for Energy Efficiency” Asia Pacific Design Automation Conference (ASP-DAC), pp. 625-625, January 2010 (Invited paper)
  36. J. P. Kulkarni, C. Augustine, B. Jung and K. Roy, “Nano-Spiral Inductors for Low Power Digital Spintronic Circuits” International Magnetics Conference (INTERMAG), January 2010
  37. M. Meterelliyoz, J. P. Kulkarni and K. Roy, “Analysis of SRAM and eDRAM Cache Memories under Spatial Temperature Variations” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), pp. 2-13, Vol. 29, Issue 1, January 2010
  38. K. Roy, J. Kulkarni and M.E. Hwang, “Low Voltage Process Adaptive Logic and Memory Arrays for Ultra-low Power Sensor Nodes” 8th IEEE Sensors Conference (Sensors), pp. 185-188, October 2009 (Invited paper)
  39. A. Goel, P. Ndai, J. P. Kulkarni and K. Roy, “Read/Access-Preferred (REAP) SRAM – Architecture-Aware Bit Cell Design for Improved Yield and Lower Vmin” Custom Integrated Circuits Conference (CICC), September 2009
  40. K. Roy, J.P. Kulkarni, S. Gupta, “Device/Circuit Interactions at 22nm Technology node” Design Automation Conference (DAC), pp.97-102, July 2009
  41. J. P. Kulkarni and K. Roy, “Process Variation Tolerant SRAM Design for Ultra Low Voltage Applications” SRC TECHCON, November 2008 (Best paper in session Award)
  42. J. P. Kulkarni and K. Roy, “Technology Circuit Co-design for Ultra-Fast InSb Quantum Well Transistors”, IEEE Transactions on Electron Devices (TED), pp. 2537-2545, Vol. 55, October 2008 [Paper]
  43. K. Roy, J.P. Kulkarni and M.E. Hwang, “Process Adaptive Digital Sub-threshold Logic and Memory” 16th International Conference on Very Large Scale Integration (VLSI-SOC), pp. 42-45, October 2008 (Invited paper)
  44. M. Meterolliyez, P. Song, F. Stellari, J. P. Kulkarni and K. Roy, “A High Sensitivity Process Variation Sensor utilizing Sub-threshold operation” Custom Integrated Circuits conference (CICC), pp. 125-128, September 2008
  45. M. Meterolliyez, J. P. Kulkarni and K. Roy, “Thermal Analysis of 8-T SRAM for Nano-scaled Technologies” International Symposium on Low Power Electronics Design, (ISLPED), pp. 123-128, August 2008
  46. Q. Cao, H.-S. Kim, N. Pimparkar, J. P. Kulkarni, C. Wang, M. Shim, K. Roy, M. A. Alam and J. A. Rogers, “Medium Scale Carbon Nanotube Thin-Film Integrated Circuits on Flexible Plastic Substrates” pp. 495-500, Nature, vol. 454, 24th July 2008
  47. J. P. Kulkarni, K. Kim, S. Park and K. Roy, “Process Variation Tolerant SRAM Array for Ultra Low Voltage Applications” Design Automation Conference (DAC), pp. 108-113, June 2008
  48. J. P. Kulkarni, M. Meterolliyez, K. Roy and J. Murthy, “Nano-scaled SRAM Thermal Stability Analysis using Hierarchical Compact Thermal Models” iTHERM, pp. 999-1005, May 2008
  49. K. Roy, J.P. Kulkarni, M.E. Hwang, A. Raychowdhury and K. Kim, “Process Variation Tolerant Digital Sub-threshold Design” 33rd Annual Government Microcircuit Applications and critical Technology Conference (GOMACTech), March 2008
  50. K. Roy, J.P. Kulkarni and M.E. Hwang, “Process Tolerant Ultra-Low Voltage Digital Sub-threshold Design” 8th topical meeting on silicon monolithic integrated circuits in RF systems, (SIRF), pp.42-45 January 2008 (Invited paper)
  51. J. P. Kulkarni, K. Kim and K. Roy, “A 160mV Fully Differential Robust Schmitt Trigger based Sub-threshold SRAM” SRC TECHCON, November 2007
  52. J. P. Kulkarni, K. Kim and K. Roy, “A 160mV Robust Schmitt Trigger based Sub-threshold SRAM” IEEE Journal of Solid State Circuits (JSSC), pp. 2304-2313, Vol. 42, No. 10, October 2007 [Paper]
  53. J. P. Kulkarni, K. Kim and K. Roy, “A 160mV Fully Differential Robust Schmitt Trigger based Sub-threshold SRAM” International Symposium on Low Power Electronics Design, (ISLPED), pp. 171-176, August 2007
  54. J. P. Kulkarni and K. Roy “A High Performance Scalable Multiplexed Keeper Technique” 2007 International Symposium on Quality Electronics Design (ISQED), pp. 545-549, March 2007
  55. J. P. Kulkarni and N. Bhat, “Effect of Poly-Si Gate Depletion on Tuning Range of MOS Varactors” Device Research Conference (DRC), pp. 81-82, June 2006
  56. J. P. Kulkarni and N. Bhat, “Process Technique for Improving Tuning range in Varactors using Poly-Silicon Depletion effect” Asia Pacific Microwave Conference (APMC), December 2004
  57. J. P. Kulkarni and N. Bhat, “Process Technique for Improving Tuning range in MOS Varactors” Proceedings of the IEEE INDICON, pp. 534-537, December 2004
  58. S. Kibey, J. P. Kulkarni and P. Sarode “A fast LSF search algorithm based on inter-frame correlation in G.723.1” EURASIP Journal of Applied Signal Processing, Vol. 11, July 2004
  59. A. Pugalia, J. P. Kulkarni, N. Bhargava and N. Bhat “Single pocket Halo Sensitivity in 100nm Analog Transistor Design” Intl. Workshop on Physics of Semiconductor Devices (IWPSD), pp. 611-613, December 2003